Unterschiede
Hier werden die Unterschiede zwischen zwei Versionen angezeigt.
Nächste Überarbeitung | Vorhergehende ÜberarbeitungLetzte ÜberarbeitungBeide Seiten der Revision | ||
homecomputer:chip8:chip8interpreter [2014/06/23 11:29] – angelegt volkerp | homecomputer:chip8:chip8interpreter [2017/08/15 06:26] – volkerp | ||
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- | ====== | + | ====== |
- | Das ist der komplette(!) originale | + | Das ist der komplette(!) originale |
Quelle: VIPER-Magazin 1-02 August 1978. | Quelle: VIPER-Magazin 1-02 August 1978. | ||
+ | |||
+ | Der CHIP-8-Interpreter ist extrem platzsparend programmiert, | ||
+ | |||
+ | |||
+ | ===== CDP 1802 ===== | ||
+ | |||
+ | |||
+ | Das Handbuch zum COSMAC VIP enthält auch das Datenblatt zum Prozessor CDP 1802 incl. Befehlsliste. | ||
+ | |||
+ | |||
+ | * http:// | ||
+ | * http:// | ||
+ | |||
+ | |||
+ | COSMAC Register Summary | ||
+ | |||
+ | < | ||
+ | D 8 Bits Data Register (Accumulator) | ||
+ | N 4 Bits Holds Low-Order Instr. Digit | ||
+ | DF 1 Bit Data Flag (ALU Carry) | ||
+ | I 4 Bits Holds High-Order Instr. Digit | ||
+ | R 16 Bits 1 of 16 Scratchpad Registers | ||
+ | R0.1 R0.0 | ||
+ | R1.1 R1.0 | ||
+ | ... | ||
+ | RF.1 RF.0 | ||
+ | T 8 Bits Holds old X, P after Interrupt (X is high byte) | ||
+ | P 4 Bits Designates which register is Program Counter | ||
+ | zeigt auf Registerarray | ||
+ | IE 1 Bit Interrupt Enable | ||
+ | X 4 Bits Designates which register is Data Pointer | ||
+ | zeigt auf Registerarray | ||
+ | Q 1 Bit Output Flip Flop | ||
+ | </ | ||
+ | |||
+ | instruction set | ||
+ | < | ||
+ | MNEM NAME OPCODE | ||
+ | ADC Add with Carry 74 | ||
+ | ADCI b Add with Carry Immediate | ||
+ | ADD | ||
+ | ADI b Add Immediate | ||
+ | AND | ||
+ | ANI b AND Immediate | ||
+ | B1 a Branch on External Flag 1 34 aa | ||
+ | B2 a Branch on External Flag 2 35 aa | ||
+ | B3 a Branch on External Flag 3 36 aa | ||
+ | B4 a Branch on External Flag 4 37 aa | ||
+ | BDF a | ||
+ | BN1 a | ||
+ | BN2 a | ||
+ | BN3 a | ||
+ | BN4 a | ||
+ | BNF a | ||
+ | BNQ a | ||
+ | BNZ a | ||
+ | BQ a Branch if Q is on 31 aa | ||
+ | BR a Branch unconditionally | ||
+ | BZ a Branch on Zero 32 aa | ||
+ | DEC r | ||
+ | DIS | ||
+ | GHI r Get High byte of Register | ||
+ | GLO r Get Low byte of Register | ||
+ | IDL | ||
+ | INC r | ||
+ | INP p Input to memory and D (for p = 9 to F) 6p | ||
+ | IRX | ||
+ | LBDF aa Long Branch if DF is 1 C3 aaaa | ||
+ | LBNF aa Long Branch if DF is 0 CB aaaa | ||
+ | LBNQ aa Long Branch if Q is off C9 aaaa | ||
+ | LBNZ aa Long Branch if Not Zero CA aaaa | ||
+ | LBQ aa Long Branch if Q is on C1 aaaa | ||
+ | LBR aa Long Branch unconditionally | ||
+ | LBZ aa Long Branch if Zero C2 aaaa | ||
+ | LDA r Load D and Advance | ||
+ | LDI b Load D Immediate | ||
+ | LDN r Load D via N (for r = 1 to F) 0r | ||
+ | LDX Load D via R(X) F0 | ||
+ | LDXA Load D via R(X) and Advance | ||
+ | LSDF Long Skip if DF is 1 CF | ||
+ | LSIE Long Skip if Interrupts Enabled | ||
+ | LSKP Long Skip C8 | ||
+ | LSNF Long Skip if DF is 0 C7 | ||
+ | LSNQ Long Skip if Q is off C5 | ||
+ | LSNZ Long Skip if Not Zero C6 | ||
+ | LSQ Long Skip if Q is on CD | ||
+ | LSZ Long Skip if Zero CE | ||
+ | MARK Save X and P in T 79 | ||
+ | NOP No Operation | ||
+ | OR Logical OR F1 | ||
+ | ORI b OR Immediate | ||
+ | OUT p | ||
+ | PHI r Put D in High byte of register | ||
+ | PLO r Put D in Low byte of register | ||
+ | REQ Reset Q 7A | ||
+ | RET | ||
+ | SAV Save T 78 | ||
+ | SD Subtract D from memory | ||
+ | SDB | ||
+ | SDBI b Subtract D with Borrow, Immediate | ||
+ | SDI b | ||
+ | SEP r Set P Dr | ||
+ | SEQ Set Q 7B | ||
+ | SEX r Set X Er | ||
+ | SHL Shift D Left FE | ||
+ | SHLC Shift D Left with Carry 7E | ||
+ | SHR Shift D Right F6 | ||
+ | SHRC Shift D Right with Carry 76 | ||
+ | SKP Skip one byte 38 | ||
+ | SM Subtract Memory from D F7 | ||
+ | SMB | ||
+ | SMBI b Subtract Memory with Borrow, Immediate | ||
+ | SMI b | ||
+ | STR r Store D into memory | ||
+ | STXD Store D via R(X) and Decrement | ||
+ | XOR | ||
+ | XRI b | ||
+ | </ | ||
+ | |||
+ | |||
+ | ===== Interpreter ===== | ||
+ | |||
< | < | ||
Zeile 266: | Zeile 388: | ||
0104: 00 IDL | 0104: 00 IDL | ||
- | ; FINAL DECODING OF " | + | ; FINAL DECODING OF " |
0105: 45 LDA R5 ; Load via R5 and advance (2nd byte of CHIP 8 instruction) | 0105: 45 LDA R5 ; Load via R5 and advance (2nd byte of CHIP 8 instruction) | ||
Zeile 602: | Zeile 724: | ||
; required--CHIP 8 instructions may alter these register settings, as indicated | ; required--CHIP 8 instructions may alter these register settings, as indicated | ||
; above. | ; above. | ||
- | ; *: In hasic VIP system with 2K RAM, 0X = 07 and 0Y = 06. In general, | + | ; *: In basic VIP system with 2K RAM, 0X = 07 and 0Y = 06. In general, |
; 0X, is highest memory page and 0Y = 0X-1. | ; 0X, is highest memory page and 0Y = 0X-1. | ||
</ | </ | ||